I am a VLSI Verification Engineer with hands-on experience in SystemVerilog, UVM, and functional verification of complex protocols. I have worked extensively on APB, AHB, AXI, SPI, and I2C protocol verification with a strong focus on constrained-random testing, assertions, scoreboarding, and functional coverage closure.
I am a VLSI Verification Engineer with hands-on experience in SystemVerilog, UVM, and functional verification of complex protocols. I have worked extensively on APB, AHB, AXI, SPI, and I2C protocol verification with a strong focus on constrained-random testing, assertions, scoreboarding, and functional coverage closure.
My goal is to deliver high-quality, thoroughly verified silicon through meticulous verification practices, comprehensive coverage analysis, and RTL debugging. I thrive in collaborative environments and enjoy solving challenging verification scenarios and waveform analysis challenges.
6 months Professional VLSI Verification Training & Protocol Implementation
UVM Verification, Protocol Testbenches, Coverage Closure
AXI 3, AHB, APB, SPI, I2C & EEPROM
VCS, QuestaSim, ModelSim, Vivado, EDA Playground
Built a complete AXI UVM environment with driver, monitor, agent, sequencer, scoreboard, predictor, and functional coverage. Developed directed and constrained-random tests for fixed, increment, wrap, error, and reset scenarios.
Built both SystemVerilog testbench and complete UVM environment including driver, monitor, agent, predictor, scoreboard, and functional coverage. Developed tests for read, write, reset, zero-wait, SLVERR scenarios.
Built structured SystemVerilog verification environment with driver, monitor, generator, scoreboard, and functional coverage. Developed nine directed testcases covering read, write, burst, and increment operations.
RTL design and complete verification suite for I2C master controller with EEPROM communication and edge case handling.
Built SPI Master and Slave RTL modules implementing shift-register-based serial communication with CPOL/CPHA modes. Developed SystemVerilog testbench to test MOSI/MISO data transfers and chip-select operation.
Designed and verified a 4-bit priority encoder using Verilog/SystemVerilog and UVM. Built key UVM components, performed simulation and debugging on EDA Playground with 100% pass results.
GPA: 8.27/10 (82.7%)
GPA: 85.5%
GPA: 88.32%
Email: mahendar20r@gmail.com
LinkedIn: linkedin.com/in/mahendar-r-155684265